1. Field of the Invention
The invention relates to systems and methods for accessing memory subsystems connected to time-shared busses other than a time-shared bus to which a requesting subsystem is connected.
2. Description of the Prior Art
Random access memory capacity is a fundamental parameter of the performance capability of any data processing system. Many data processing systems are capable of handling several optional sizes of random access memories as part of the system. Further, many data processing systems have the facility to accept additional random access memory in the form of freestanding units. Many data processing systems further include a number of subsystems which utilize a plurality of intercommunication busses which can be time-shared among the various subsystems. Random access memory subsystems and various other subsystems are typically connected to each such intercommunications bus. One such system is described in U.S. Pat. No. 4,041,472, issued Aug. 9, 1977, entitled "SYSTEM AND METHOD FOR SHARING MEMORY," assigned to the same Assignee as the present invention, and hereinafter referred to as the Shah patent. The Shah patent describes a system involving at least two pairs of interbus communications adaptors to accomplish interbus communication between a requesting subsystem connected to one bus and a memory subsystem connected to another bus, thereby permitting a subsystem connected to one bus to, in effect, expand the amount of random access memory available to that subsystem by accessing not only memory connected to that bus, but also random access memory connected to other intercommunication busses in the same system. The described system avoids the cost of connecting additional free-standing random access memory units to a particular intercommunications bus to which a subsystem requiring additional memory capacity is connected, if memory capacity is available on other intercommunication busses of the same system. However, the system described in the Shah patent requires separate pairs of interbus communication adaptors for the request messages and corresponding response messages between a requesting subsystem and a memory subsystem.